#define CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select 0 */ #define CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select 1 */ #define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select 0 */ #define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select 1 */ #define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select 0 */ #define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select 1 */ #define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select 2 */ #define ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */ #define SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */ #define SHS0 (0x0400u) /* ADC12 Sample/Hold Source 0 */ #define SHS1 (0x0800u) /* ADC12 Sample/Hold Source 1 */ #define CSTARTADD0 (0x1000u) /* ADC12 Conversion Start Address 0 */ #define CSTARTADD1 (0x2000u) /* ADC12 Conversion Start Address 1 */ #define CSTARTADD2 (0x4000u) /* ADC12 Conversion Start Address 2 */ #define CSTARTADD3 (0x8000u) /* ADC12 Conversion Start Address 3 */
#define CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */ #define CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */ #define CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */ #define CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */ #define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */ #define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */ #define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */ #define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */ #define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */ #define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */ #define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */ #define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */ #define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */ #define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */ #define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */ #define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */ #define SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */ #define SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */ #define SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */ #define SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */ #define CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */ #define CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */ #define CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */ #define CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */ #define CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */ #define CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */ #define CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */ #define CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
#define CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */ #define CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */ #define CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */ #define CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */ #define CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */ #define CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */ #define CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */ #define CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
/* ADC12MCTLx */
#define INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */ #define INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */ #define INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */ #define INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */ #define SREF0 (0x0010u) /* ADC12 Select Reference Bit 0 */ #define SREF1 (0x0020u) /* ADC12 Select Reference Bit 1 */ #define SREF2 (0x0040u) /* ADC12 Select Reference Bit 2 */ #define EOS (0x0080u) /* ADC12 End of Sequence */
#define INCH_0 (0) /* ADC12 Input Channel 0 */ #define INCH_1 (1) /* ADC12 Input Channel 1 */ #define INCH_2 (2) /* ADC12 Input Channel 2 */ #define INCH_3 (3) /* ADC12 Input Channel 3 */ #define INCH_4 (4) /* ADC12 Input Channel 4 */ #define INCH_5 (5) /* ADC12 Input Channel 5 */ #define INCH_6 (6) /* ADC12 Input Channel 6 */ #define INCH_7 (7) /* ADC12 Input Channel 7 */ #define INCH_8 (8) /* ADC12 Input Channel 8 */ #define INCH_9 (9) /* ADC12 Input Channel 9 */ #define INCH_10 (10) /* ADC12 Input Channel 10 */ #define INCH_11 (11) /* ADC12 Input Channel 11 */ #define INCH_12 (12) /* ADC12 Input Channel 12 */ #define INCH_13 (13) /* ADC12 Input Channel 13 */ #define INCH_14 (14) /* ADC12 Input Channel 14 */ #define INCH_15 (15) /* ADC12 Input Channel 15 */
#define SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */ #define SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */ #define SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */ #define SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */ #define SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */ #define SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */ #define SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */ #define SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
/* ADC12IV Definitions */
#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */ #define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */ #define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */ #define ADC12IV_ADC12IFG0 (0x0006u) /* ADC12IFG0 */ #define ADC12IV_ADC12IFG1 (0x0008u) /* ADC12IFG1 */ #define ADC12IV_ADC12IFG2 (0x000Au) /* ADC12IFG2 */ #define ADC12IV_ADC12IFG3 (0x000Cu) /* ADC12IFG3 */ #define ADC12IV_ADC12IFG4 (0x000Eu) /* ADC12IFG4 */ #define ADC12IV_ADC12IFG5 (0x0010u) /* ADC12IFG5 */ #define ADC12IV_ADC12IFG6 (0x0012u) /* ADC12IFG6 */ #define ADC12IV_ADC12IFG7 (0x0014u) /* ADC12IFG7 */ #define ADC12IV_ADC12IFG8 (0x0016u) /* ADC12IFG8 */ #define ADC12IV_ADC12IFG9 (0x0018u) /* ADC12IFG9 */ #define ADC12IV_ADC12IFG10 (0x001Au) /* ADC12IFG10 */ #define ADC12IV_ADC12IFG11 (0x001Cu) /* ADC12IFG11 */ #define ADC12IV_ADC12IFG12 (0x001Eu) /* ADC12IFG12 */ #define ADC12IV_ADC12IFG13 (0x0020u) /* ADC12IFG13 */ #define ADC12IV_ADC12IFG14 (0x0022u) /* ADC12IFG14 */ #define ADC12IV_ADC12IFG15 (0x0024u) /* ADC12IFG15 */
/************************************************************ * Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define PORT2_VECTOR (1 * 2u) /* 0xFFE2 Port 2 */
#define USART1TX_VECTOR (2 * 2u) /* 0xFFE4 USART 1 Transmit */ #define USART1RX_VECTOR (3 * 2u) /* 0xFFE6 USART 1 Receive */ #define PORT1_VECTOR (4 * 2u) /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR (5 * 2u) /* 0xFFEA Timer A CC1-2, TA */ #define TIMERA0_VECTOR (6 * 2u) /* 0xFFEC Timer A CC0 */ #define ADC12_VECTOR (7 * 2u) /* 0xFFEE ADC */
#define USART0TX_VECTOR (8 * 2u) /* 0xFFF0 USART 0 Transmit */ #define USART0RX_VECTOR (9 * 2u) /* 0xFFF2 USART 0 Receive */ #define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */ #define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */ #define TIMERB1_VECTOR (12 * 2u) /* 0xFFF8 Timer B CC1-6, TB */ #define TIMERB0_VECTOR (13 * 2u) /* 0xFFFA Timer B CC0 */ #define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maskable */
#define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */
#define UART1TX_VECTOR USART1TX_VECTOR #define UART1RX_VECTOR USART1RX_VECTOR
#define UART0TX_VECTOR USART0TX_VECTOR #define UART0RX_VECTOR USART0RX_VECTOR #define ADC_VECTOR ADC12_VECTOR
/************************************************************ * End of Modules
************************************************************/ #pragma language=default
#endif /* #ifndef __msp430x14x */
