#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ #define CARSEL (0x40) /* Comp. A Internal Reference Enable */ #define CAEX (0x80) /* Comp. A Exchange Inputs */
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ #define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ #define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ #define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT (0x01) /* Comp. A Output */
#define CAF (0x02) /* Comp. A Enable Output Filter */
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */ #define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */ #define CACTL24 (0x10) #define CACTL25 (0x20) #define CACTL26 (0x40) #define CACTL27 (0x80)
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ #define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ #define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ #define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ #define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ #define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ #define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ #define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
/************************************************************ * ADC12
************************************************************/
#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */
#define ADC12CTL0_ (0x01A0u) /* ADC12 Control 0 */ DEFW( ADC12CTL0 , ADC12CTL0_)
#define ADC12CTL1_ (0x01A2u) /* ADC12 Control 1 */ DEFW( ADC12CTL1 , ADC12CTL1_)
#define ADC12IFG_ (0x01A4u) /* ADC12 Interrupt Flag */ DEFW( ADC12IFG , ADC12IFG_)
#define ADC12IE_ (0x01A6u) /* ADC12 Interrupt Enable */ DEFW( ADC12IE , ADC12IE_)
#define ADC12IV_ (0x01A8u) /* ADC12 Interrupt Vector Word */ DEFW( ADC12IV , ADC12IV_)
#define ADC12MEM_ (0x0140u) /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC__
#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */ #else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif
#define ADC12MEM0_ (0x0140u) /* ADC12 Conversion Memory 0 */ DEFW( ADC12MEM0 , ADC12MEM0_)
#define ADC12MEM1_ (0x0142u) /* ADC12 Conversion Memory 1 */ DEFW( ADC12MEM1 , ADC12MEM1_)
#define ADC12MEM2_ (0x0144u) /* ADC12 Conversion Memory 2 */ DEFW( ADC12MEM2 , ADC12MEM2_)
#define ADC12MEM3_ (0x0146u) /* ADC12 Conversion Memory 3 */ DEFW( ADC12MEM3 , ADC12MEM3_)
#define ADC12MEM4_ (0x0148u) /* ADC12 Conversion Memory 4 */ DEFW( ADC12MEM4 , ADC12MEM4_)
#define ADC12MEM5_ (0x014Au) /* ADC12 Conversion Memory 5 */ DEFW( ADC12MEM5 , ADC12MEM5_)
#define ADC12MEM6_ (0x014Cu) /* ADC12 Conversion Memory 6 */ DEFW( ADC12MEM6 , ADC12MEM6_)
#define ADC12MEM7_ (0x014Eu) /* ADC12 Conversion Memory 7 */ DEFW( ADC12MEM7 , ADC12MEM7_)
#define ADC12MEM8_ (0x0150u) /* ADC12 Conversion Memory 8 */ DEFW( ADC12MEM8 , ADC12MEM8_)
#define ADC12MEM9_ (0x0152u) /* ADC12 Conversion Memory 9 */ DEFW( ADC12MEM9 , ADC12MEM9_)
#define ADC12MEM10_ (0x0154u) /* ADC12 Conversion Memory 10 */ DEFW( ADC12MEM10 , ADC12MEM10_)
#define ADC12MEM11_ (0x0156u) /* ADC12 Conversion Memory 11 */ DEFW( ADC12MEM11 , ADC12MEM11_)
#define ADC12MEM12_ (0x0158u) /* ADC12 Conversion Memory 12 */ DEFW( ADC12MEM12 , ADC12MEM12_)
#define ADC12MEM13_ (0x015Au) /* ADC12 Conversion Memory 13 */ DEFW( ADC12MEM13 , ADC12MEM13_)
#define ADC12MEM14_ (0x015Cu) /* ADC12 Conversion Memory 14 */ DEFW( ADC12MEM14 , ADC12MEM14_)
#define ADC12MEM15_ (0x015Eu) /* ADC12 Conversion Memory 15 */ DEFW( ADC12MEM15 , ADC12MEM15_)
#define ADC12MCTL_ (0x0080u) /* ADC12 Memory Control */ #ifndef __IAR_SYSTEMS_ICC__
#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */ #else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ #endif
#define ADC12MCTL0_ (0x0080u) /* ADC12 Memory Control 0 */ DEFC( ADC12MCTL0 , ADC12MCTL0_)
#define ADC12MCTL1_ (0x0081u) /* ADC12 Memory Control 1 */ DEFC( ADC12MCTL1 , ADC12MCTL1_)
#define ADC12MCTL2_ (0x0082u) /* ADC12 Memory Control 2 */ DEFC( ADC12MCTL2 , ADC12MCTL2_)
#define ADC12MCTL3_ (0x0083u) /* ADC12 Memory Control 3 */ DEFC( ADC12MCTL3 , ADC12MCTL3_)
#define ADC12MCTL4_ (0x0084u) /* ADC12 Memory Control 4 */ DEFC( ADC12MCTL4 , ADC12MCTL4_)
#define ADC12MCTL5_ (0x0085u) /* ADC12 Memory Control 5 */ DEFC( ADC12MCTL5 , ADC12MCTL5_)
#define ADC12MCTL6_ (0x0086u) /* ADC12 Memory Control 6 */ DEFC( ADC12MCTL6 , ADC12MCTL6_)
#define ADC12MCTL7_ (0x0087u) /* ADC12 Memory Control 7 */ DEFC( ADC12MCTL7 , ADC12MCTL7_)
#define ADC12MCTL8_ (0x0088u) /* ADC12 Memory Control 8 */ DEFC( ADC12MCTL8 , ADC12MCTL8_)
#define ADC12MCTL9_ (0x0089u) /* ADC12 Memory Control 9 */ DEFC( ADC12MCTL9 , ADC12MCTL9_)
#define ADC12MCTL10_ (0x008Au) /* ADC12 Memory Control 10 */ DEFC( ADC12MCTL10 , ADC12MCTL10_)
#define ADC12MCTL11_ (0x008Bu) /* ADC12 Memory Control 11 */ DEFC( ADC12MCTL11 , ADC12MCTL11_)
#define ADC12MCTL12_ (0x008Cu) /* ADC12 Memory Control 12 */ DEFC( ADC12MCTL12 , ADC12MCTL12_)
#define ADC12MCTL13_ (0x008Du) /* ADC12 Memory Control 13 */ DEFC( ADC12MCTL13 , ADC12MCTL13_)
#define ADC12MCTL14_ (0x008Eu) /* ADC12 Memory Control 14 */ DEFC( ADC12MCTL14 , ADC12MCTL14_)
#define ADC12MCTL15_ (0x008Fu) /* ADC12 Memory Control 15 */ DEFC( ADC12MCTL15 , ADC12MCTL15_)
/* ADC12CTL0 */
#define ADC12SC (0x001) /* ADC12 Start Conversion */ #define ENC (0x002) /* ADC12 Enable Conversion */
#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */ #define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */ #define ADC12ON (0x010) /* ADC12 On/enable */ #define REFON (0x020) /* ADC12 Reference on */ #define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */ #define MSC (0x080) /* ADC12 Multiple SampleConversion */ #define SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select 0 */ #define SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select 1 */
#define SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select 2 */ #define SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select 3 */ #define SHT10 (0x1000u) /* ADC12 Sample Hold 0 Select 0 */ #define SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select 1 */ #define SHT12 (0x4000u) /* ADC12 Sample Hold 2 Select 2 */ #define SHT13 (0x8000u) /* ADC12 Sample Hold 3 Select 3 */ #define MSH (0x080)
#define SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ #define SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */ #define SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */ #define SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */ #define SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */ #define SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */ #define SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */ #define SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */ #define SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */ #define SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */ #define SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */ #define SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */ #define SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */ #define SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */ #define SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */ #define SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
#define SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ #define SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ #define SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ #define SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ #define SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */ #define SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */ #define SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */ #define SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */ #define SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */ #define SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */ #define SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */ #define SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */ #define SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */ #define SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */ #define SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */ #define SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
/* ADC12CTL1 */
#define ADC12BUSY (0x0001u) /* ADC12 Busy */
