BEGINPR01:PROCESS(CLK0)BEGIN
IFCLK‘EVENTANDCLK=’1’THENQ<=NOT(CLORQ);ELSEENDIF;
ENDPROCESS;PR02:PROCESS(CLK0)BEGINOUT1<=Q;ENDPROCESS;
ENDARCHITECTUREONE;ENDPROCESS;
4-5.给出1位全减器的VHDL描述。要求：
(1)首先设计1位半减器，然后用例化语句将它们连接起来，图3-32中h_suber是半减器，diff是输出差，s_out是借位输出，sub_in是借位输入。
(2)以1位全减器为基本硬件，构成串行借位的8位减法器，要求用例化语句来完成此项设计(减法运算是x–y-sun_in=diffr)4-5.答案
底层文件1：or2a.VHD实现或门操作LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYor2aIS
PORT(a,b:INSTD_LOGIC;
c:OUTSTD_LOGIC);
ENDENTITYor2a;
ARCHITECTUREoneOFor2aISBEGIN
c<=aORb;
ENDARCHITECTUREone;
底层文件2：h_subber.VHD实现一位半减器LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYh_subberISPORT(x,y:INSTD_LOGIC;
diff,s_out::OUTSTD_LOGIC);ENDENTITYh_subber;
ARCHITECTUREONEOFh_subberIS
SIGNALxyz:STD_LOGIC_VECTOR(1DOWNTO0);BEGIN
xyz<=x&y;PROCESS(xyz)BEGIN
CASExyzIS
WHEN\=>diff<='0';s_out<='0';WHEN\=>diff<='1';s_out<='1';WHEN\=>diff<='1';s_out<='0';
WHEN\=>diff<='0';s_out<='0';WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;
ENDARCHITECTUREONE;
顶层文件：f_subber.VHD实现一位全减器LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYf_subberIS
PORT(x,y,sub_in:INSTD_LOGIC;diffr,sub_out:OUTSTD_LOGIC);ENDENTITYf_subber;
ARCHITECTUREONEOFf_subberISCOMPONENTh_subberPORT(x,y:INSTD_LOGIC;diff,S_out:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2a
PORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENT;
SIGNALd,e,f:STD_LOGIC;BEGIN
u1:h_subberPORTMAP(x=>x,y=>y,diff=>d,s_out=>e);
u2:h_subberPORTMAP(x=>d,y=>sub_in,diff=>diffr,s_out=>f);u3:or2aPORTMAP(a=>f,b=>e,c=>sub_out);ENDARCHITECTUREONE;ENDARCHITECTUREART;
4-6.根据下图，写出顶层文件MX3256.VHD的VHDL设计文件。4-6.答案
MAX3256顶层文件LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMAX3256IS
PORT(INA,INB,INCK:INSTD_LOGIC;INC:INSTD_LOGIC;E,OUT:OUTSTD_LOGIC);ENDENTITYMAX3256;
ARCHITECTUREONEOFMAX3256ISCOMPONENTLK35--调用LK35声明语句PORT(A1,A2:INSTD_LOGIC;CLK:INSTD_LOGIC;Q1,Q2:OUTSTD_LOGIC);ENDCOMPONENT;
COMPONENTD--调用D触发器声明语句PORT(D,C:INSTD_LOGIC;
CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDCOMPONENT;
COMPONENTMUX21--调用二选一选择器声明语句PORT(B,A:INSTD_LOGIC;S:INSTD_LOGIC;C:OUTSTD_LOGIC);ENDCOMPONENT;
SIGNALAA,BB,CC,DD:STD_LOGIC;BEGIN
u1:LK35PORTMAP(A1=>INA,A2=>INB,CLK=INCK,Q1=>AA,Q2=>BB);u2:DPORTMAP(D=>BB;CLK=>INCK,C=>INC,Q=>CC);
u3:LK35PORTMAP(A1=>BB,A2=>CC,CLK=INCK,Q1=>DD,Q2=>OUT1)；u4:MUX21PORTMAP(B=>AA,A=>DD,S=>BB,C=>E);ENDARCHITECTUREONE;
设计含有异步清零和计数使能的16位二进制加减可控计数器。4-7.答案：LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT16IS
PORT(CLK,RST,EN:INSTD_LOGIC;
CHOOSE:INBIT;
SETDATA:BUFFERINTEGERRANCE65535DOWNTO0;COUT:BUFFERINTEGERRANCE65535DOWNTO0);ENDCNT16;
ARCHITECTUREONEOFCNT16ISBEGIN
PROCESS(CLK,RST,SDATA)
VARIABLEQI:STD_LOGIC_VECTOR(65535DOWNTO0);BEGIN
IFRST='1'THEN--计数器异步复位
QI:=(OTHERS=>'0');
ELSIFSET=’1’THEN--计数器一步置位QI:=SETDATA;
ELSIFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿
IFEN=’1’THEN–检测是否允许计数
IFCHOOSE=’1’THEN--选择加法计数
QI:=QI+1;--计数器加一ELSEQI=QI-1;--计数器加一ENDIF;
ENDIF;ENDIF;
COUT<=QI;--将计数值向端口输出ENDPROCESS;ENDONE;
第五章
5-1归纳利用QuartusII进行VHDL文本输入设计的流程：从文件输入一直到SignalTapII测试。P95~P115
答：1建立工作库文件夹和编辑设计文件；2创建工程；3编译前设置；4全程编译；5时序仿真；6引脚锁定；7配置文件下载；8打开SignalTapII编辑窗口；9调入SignalTapII的待测信号；10SignalTapII参数设置；11SignalTapII参数设置文件存盘；12带有SignalTapII测试信息的编译下载；13启动SignalTapII进行采样与分析；14SignalTapII的其他设置和控制方法。5.6
5.7
