SCOUNT10<=\ELSE
CN<='0';
SCOUNT10<=SCOUNT10+'1'; END IF; END IF; END IF;
END PROCESS; END ART;
六进制计数器的源程序（CDU6.VDH） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU6 IS
PORT( CLK,CLR,EN:IN STD_LOGIC; CN :OUT STD_LOGIC;
COUNT6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CDU6;
ARCHITECTURE ART OF CDU6 IS
SIGNAL SCOUNT6: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
COUNT6<=SCOUNT6;
PROCESS (CLK,CLR,EN) BEGIN
IF(CLR='1')THEN
SCOUNT6<=\ELSIF RISING_EDGE(CLK) THEN IF(EN='1')THEN
IF SCOUNT6=\CN<='1';
SCOUNT6<=\ELSE
CN<='0';
SCOUNT6<=SCOUNT6+'1'; END IF; END IF; END IF;
END PROCESS; END ART;
计数器的源程序（COUNT.VHD） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT IS
PORT( CLK,CLR,EN:IN STD_LOGIC;
S_1MS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_10MS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_100MS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_1S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_10S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_1MIN:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_10MIN:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HOUR:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COUNT;
ARCHITECTURE ART OF COUNT IS COMPONENT CDU10
PORT( CLK,CLR,EN:IN STD_LOGIC; CN :OUT STD_LOGIC;
COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT CDU10; COMPONENT CDU6
PORT( CLK,CLR,EN:IN STD_LOGIC; CN :OUT STD_LOGIC;
COUNT6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT CDU6;
SIGNAL A,B,C,D,E,F,G,H:STD_LOGIC; BEGIN
UL:CDU10 PORT MAP (CLK,CLR,EN,A,S_1MS); U2:CDU10 PORT MAP (A,CLR,EN,B,S_10MS); U3:CDU10 PORT MAP (B,CLR,EN,C,S_100MS); U4:CDU10 PORT MAP (C,CLR,EN,D,S_1S); U5:CDU6 PORT MAP (D,CLR,EN,E,S_10S); U6:CDU10 PORT MAP (E,CLR,EN,F,S_1MIN); U7:CDU6 PORT MAP (F,CLR,EN,G,S_10MIN); U8:CDU10 PORT MAP (G,CLR,EN,H,HOUR); END ART;
4. 显示模块的源程序
数据选择器的源程序（MULX.VDH）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MULX IS
PORT( CLK,CLR,EN:IN STD_LOGIC;
S_1MS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10MS:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_100MS:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_1S:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_10S:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_1MIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_10MIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); HOUR:IN STD_LOGIC_VECTOR(3 DOWNTO 0); OUTBCD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END MULX;
ARCHITECTURE ART OF MULX IS
SIGNAL COUNT :STD_LOGIN_VECTOR(3 DOWNTO 0); BEGIN
PROCESS (CLK) BEGIN
IF CLR='1'THEN COUNT<=\
ELSIF RISING_EDGE(CLK)THEN IF EN ='1' THEN COUNT<=\ELSE
COUNT<=COUNT+'1'; END IF; END IF; END IF;
END PROCESS; PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1' THEN CASE COUNT IS
WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN OTHERS=>OUTBCD<=\END CASE; END IF;
END PROCESS;
END ART;
BCD七段译码器驱动器的源程序（BCD7.VDH）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BCD7 IS PORT(
BCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END BCD7;
ARCHITECTURE ART OF BCD7 IS BEGIN
LED<=\\\\\\\\\\\END ART；
5. 顶层设计的源程序（MB.VHD） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MB IS
PORT( SP,CLR,CLK:IN STD_LOGIC; CO,EN: OUT STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); OUTBCD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END MB;
ARCHITECTURE ART OF MB IS COMPONENT CTRL
PORT( CLK,CLR,SP:IN STD_LOGIC; EN :OUT STD_LOGIC); END COMPONENT ;
