.
(
CLK : in std_logic );
end top;
architecture Behavioral of top is signal a0:std_logic; signal irq:std_logic;
signal d1:std_logic_vector(7 downto 0); signal d2:std_logic_vector(7 downto 0); signal rw:std_logic; signal rdy:std_logic;
signal pd:std_logic_vector(7 downto 0); signal tr:std_logic;
component processor port (
clk : in std_logic; IRQ : in std_logic;
DOUT : out std_logic_vector(7 downto 0):=\RW : out std_logic:='0';--0read,1write A0 : out std_logic:='0';--0sr,1br
DIN : in std_logic_vector(7 downto 0) );
end component;
component poc port (
A0 : in std_logic; RW : in std_logic; clk : in std_logic; CS : in std_logic:='1'; RDY : in std_logic;
IRQ : out std_logic:='1';
DOUT : out std_logic_vector(7 downto 0); PD : out std_logic_vector(7 downto 0); TR : out std_logic:='0';
DIN : in std_logic_vector(7 downto 0) );
end component;
word资料
.
component print port (
RDY : out std_logic:='1'; TR : in std_logic;
PD : in std_logic_vector(7 downto 0); clk : in std_logic );
end component; begin
u1: processor port map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d1,DIN=>d2); u2: poc port
map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d2,DIN=>d1,RDY=>rdy,TR=>tr,PD=>pd);
u3: print port map(clk=>CLK,RDY=>rdy,TR=>tr,PD=>pd); end Behavioral;
word资料
