BEGIN setstart<='0';clrstart<='0'; CASE state3 IS WHEN s_cancel=> IF(start_cancel_rising='1')THEN nextstate3<=s_start;setstart<='1'; ELSE
nextstate3<=s_cancel;clrstart<='1';
END IF;
WHEN s_start=> IF(timer_down_rising='1')THEN clrstart<='1';nextstate3<=s_cancel; ELSIF(start_cancel_rising='1')THEN nextstate3<=s_cancel;clrstart<='1'; ELSE
nextstate3<=s_start;
END IF;
END CASE;
END PROCESS;
main_control_update:PROCESS(reset,sysclk,timer_down_rising)IS BEGIN IF(reset='0')THEN
state1<=s_type1;state2<=s_quan1;state3<=s_cancel;
ELSIF(sysclk'EVENT AND sysclk='1')THEN state1<=nextstate1;state2<=nextstate2;state3<=nextstate3;
IF(set_type1='1')THEN type1_out<='1';ELSE type1_out<='0';END IF; IF(set_type2='1')THEN type2_out<='1';ELSE type2_out<='0';END IF; IF(set_type3='1')THEN type3_out<='1';ELSE type3_out<='0';END IF; IF(set_quan1='1')THEN quan1_out<='1';ELSE quan1_out<='0';END IF; IF(set_quan2='1')THEN quan2_out<='1';ELSE quan2_out<='0';END IF; IF(set_quan3='1')THEN quan3_out<='1';ELSE quan3_out<='0';END IF; IF(timer_down_rising='1')THEN start_out<='0'; ELSIF(clrstart='1')THEN start_out<='0';
ELSIF(setstart='1')THEN start_out<='1';
END IF;
type_sel_dlayed<=type_sel;
quantity_sel_dlayed<=quantity_sel;
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start_cancel_dlayed<=start_cancel;
timer_down_dlayed<=timer_down;
END IF; END PROCESS;
END ARCHITECTURE rtl;
3.选择的定时模块
LIBRARY
IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY timer_count IS PORT(reset,sysclk,clk,start_in,ok_buy:IN STD_LOGIC;
timer_down_out:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE rtl OF timer_count IS TYPE stateTYPE IS(idle,incount); SIGNAL state,nextstate:stateTYPE;
SIGNAL count_inc,count_clr,setdown,clrdown:STD_LOGIC; SIGNAL timer_down,ok_buy_rising,ok_buy_dlayed:STD_LOGIC; SIGNAL count,count_u:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL timerdown_rising,timerdown_dlayed,clk_rising,clk_dlayed:STD_LOGIC; BEGIN
timerdown_rising<=timer_down AND (NOT timerdown_dlayed); ok_buy_rising<=ok_buy AND (NOT ok_buy_dlayed); clk_rising<=clk AND (NOT clk_dlayed);
count1:PROCESS(clk_rising,state,start_in,count,ok_buy_rising)IS BEGIN setdown<='0';clrdown<='0';count_inc<='0';count_clr<='0'; CASE state IS WHEN idle=>clrdown<='1';count_clr<='1'; IF(start_in='1' AND timerdown_rising='0')THEN
nextstate<=incount;
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ELSE
nextstate<=idle;
END IF;
WHEN incount=> IF(start_in='0' OR ok_buy_rising='1')THEN
nextstate<=idle;
ELSE IF(clk_rising='1' AND start_in='1')THEN IF(count/=count_u)THEN
count_inc<='1';nextstate<=incount;
ELSE clrdown<='0'; setdown<='1'; count_clr<='1';
nextstate<=idle;
END IF;
END IF;
END IF;
END CASE;
END PROCESS;
timer_count_update:PROCESS(reset,sysclk)IS BEGIN IF(reset='0' AND (NOT timerdown_rising)='0')THEN
state<=idle;clk_dlayed<='0';count_u<=\
ELSIF(sysclk'EVENT AND sysclk='1')THEN
state<=nextstate;
IF(clrdown='1')THEN timer_down<='0';ELSIF(setdown='1')THEN timer_down<='1';END IF; IF(count_inc='1')THEN
count<=count-1;
ELSIF(count_clr='1')THEN count<=\ END IF;
timerdown_dlayed<=timer_down; ok_buy_dlayed<=ok_buy;
clk_dlayed<=clk;
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END IF;
timer_down_out<=timer_down;
END PROCESS;
END ARCHITECTURE rtl;
，商品金额计算模块
LIBRARY
IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY money_count IS PORT(reset,sysclk,start_in,timer_down,ok_buy:IN STD_LOGIC; type1_in,type2_in,type3_in,quan1_in,quan2_in,quan3_in:IN STD_LOGIC;
money_1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
ARCHITECTURE rtl OF money_count IS
SIGNAL ok_buy_rising,ok_buy_dlayed:STD_LOGIC; SIGNAL timer_down_rising,timer_down_dlayed:STD_LOGIC; BEGIN
ok_buy_rising<=ok_buy AND (NOT ok_buy_dlayed);
timer_down_rising<=timer_down AND (NOT timer_down_dlayed);
money_count_update:PROCESS(reset,sysclk,timer_down_rising,ok_buy_rising)IS VARIABLE money_sum_tmpe:INTEGER; VARIABLE uu:STD_LOGIC; BEGIN IF(reset='0' OR timer_down_rising='1')THEN
money_sum_tmpe:=0;uu:='0';
ELSIF(sysclk'EVENT AND sysclk='1')THEN IF(ok_buy_rising='0' AND uu='0')THEN
money_sum_tmpe:=0;
ELSE uu:='1';
IF(start_in='0')THEN
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