stw r5, 0 (r6)
/*设置PPC_ACR寄存器*/ /* program the PPC_ALRH */ addis r5,0,0x0126 ori r5,r5,0x7893 lis r6, HIADJ (M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6)
/*设置PPC_ALRH寄存器*/ /* program the SIUMCR */ addis r5,0,0x0820 ori r5,r5,0x0000 lis r6, HIADJ (M8260_SIUMCR (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_SIUMCR (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6)
/*设置SIUMCR寄存器*/ /* program the TESCR1 */ addis r5,0,0x0000 ori r5,r5,0x4000 lis r6, HIADJ (M8260_TESCR1 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_TESCR1 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6)
/*设置TESCR1寄存器*/ /* program the LTESCR1 */ addis r5,0,0x0000 ori r5,r5,0x4000 lis r6, HIADJ (M8260_LTESCR1 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_LTESCR1 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6)
/*设置LTESCR1寄存器*/ /* * Map the bank 0 to the flash area - On the ADS board at reset time * the bank 0 is already used to map the flash. */
/* load the base register */
lis r5, HIADJ ((ROM_BASE_ADRS & M8260_BR_BA_MSK) | \\ M8260_BR_PS_32 | M8260_BR_V)
addi r5, r5, LO ((ROM_BASE_ADRS & M8260_BR_BA_MSK) | \\ M8260_BR_PS_32 | M8260_BR_V) lis r6, HIADJ (M8260_BR0 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_BR0 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) /* load the option register */
lis r5, HIADJ ((0xff800000 & M8260_OR_AM_MSK) M8260_OR_EHTR_8 \\
| M8260_OR_CSNT_EARLY M8260_OR_SCY_3_CLK)
addi r5, r5, LO ((0xff800000 & M8260_OR_AM_MSK) M8260_OR_EHTR_8 \\
| M8260_OR_CSNT_EARLY M8260_OR_SCY_3_CLK) lis r6, HIADJ (M8260_OR0 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_OR0 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) /* map the bank 1 to the BCSRs */ lis r5, HIADJ ((0xffff8000 & M8260_OR_AM_MSK) \\ | M8260_OR_SCY_1_CLK) addi r5, r5, LO ((0xffff8000 & M8260_OR_AM_MSK) \\ | M8260_OR_SCY_1_CLK) lis r6, HIADJ (M8260_OR1 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_OR1 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) /* write the proper value to the base register */ lis r5, HIADJ (BCSR0 | M8260_BR_PS_32 | M8260_BR_V) addi r5, r5, LO (BCSR0 | M8260_BR_PS_32 | M8260_BR_V) lis r6, HIADJ (M8260_BR1 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_BR1 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) /*内存初始化*/
SdramInit:
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/* program the MPTPR */ addi r5,0,0x4000
lis r6, HIADJ (M8260_MPTPR (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_MPTPR (INTERNAL_MEM_MAP_ADDR)) sth r5, 0x0 (r6) /* store upper half-word */ /* program the PSRT */ addi r5,0,0x0010 /* load 0x10 or 16 */
lis r6, HIADJ (M8260_PSRT (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_PSRT (INTERNAL_MEM_MAP_ADDR)) stb r5, 0x0 (r6) /* store byte - bits[24-31] */ /* load OR2 */
lis r5, HIADJ ((0xff000000 & M8260_OR_AM_MSK) | \\ M8260_OR_SDRAM_ROWST_9 \\ | M8260_OR_SDRAM_NUMR_11 M8260_OR_SDRAM_PM_NORM)
addi r5, r5, LO ((0xff000000 & M8260_OR_AM_MSK) | \\ M8260_OR_SDRAM_ROWST_9 \\ | M8260_OR_SDRAM_NUMR_11 M8260_OR_SDRAM_PM_NORM)
lis r6, HIADJ (M8260_OR2 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_OR2 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) /* load BR2 */ lis r5, HIADJ (LOCAL_MEM_LOCAL_ADRS | M8260_BR_PS_64 | \\ M8260_BR_MS_SDRAM_60X | M8260_BR_V) addi r5, r5, LO (LOCAL_MEM_LOCAL_ADRS | M8260_BR_PS_64 | \\ M8260_BR_MS_SDRAM_60X | M8260_BR_V)
lis r6, HIADJ (M8260_BR2 (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_BR2 (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) /* * program the PSDMR as explained below: * PBI is set to zero, since page-based interleaving is not * supported on early silicon revisions * Refresh services are off for now
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* OP selects the \ * SDAM = b001 * BSMA selects A15-A17 as bank select lines * A9 is selected as control pin for SDA10 on SDRAM * 7-clock refresh recovery time * precharge-to-activate interval is 3-clock time * activate-to-read/write interval is 2-clock time * Burst lenght is 4 * last data out to precharge is 1 clock * write recovery time is 1 clock * no external address multiplexing * normal timing for the control lines * CAS latency is 2 */ addis r5,0,0x296E ori r5,r5,0xB452
lis r6, HIADJ (M8260_PSDMR (INTERNAL_MEM_MAP_ADDR)) addi r6, r6, LO (M8260_PSDMR (INTERNAL_MEM_MAP_ADDR)) stw r5, 0 (r6) addis r0,0,0 /* do a single write to an arbitrary location */ addi r5,0,0x00FF /* Load 0x000000FF into r5 */ stb r5,0(r0) /* Write 0xFF to address 0 - bits [24-31] */ /* issue a \ addis r5,0,0x096E ori r5,r5,0xB452 stw r5, 0 (r6) /* Loop 8 times, writing 0xFF to address 0 */ addi r7,0,0x0008 mtspr 9,r7 /* Load spr CTR with 8 */ addi r8,0,0x00FF /* Load 0x000000FF into r8 */
SdramWrLoop: stb r8,0(r0) /* Write 0xFF to address 0 */ bc 16,0,SdramWrLoop /* Decrement CTR, and possibly branch */
