基于DDS的精密正弦信号发生器的设计
begin process(a) begin case a is
when \when \when \when \when \when \when \when \when \when \when others=>null; end case; end process; end chu_arc;
FENP模块将CHUZHI模块送来的初值对时钟进行分频，得到不同的工作频率，从而调节波形频率。
library ieee;
use ieee.std_logic_1164.all; entity fenp is
port(a:in integer range 0 to 1024; clk:in std_logic; q:out std_logic);
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基于DDS的精密正弦信号发生器的设计
end fenp;
architecture fenp_arc of fenp is begin process(clk)
variable b,d:std_logic;
variable c:integer range 0 to 1024; begin
if clk'event and clk='1'then if b='0'then c:=a-1; b:='1'; else if c=1 then b:='0'; d:=not d; else c:=c-1; end if; end if; end if; q<=d; end process; end fenp_arc;
DDS电路的 VHDL设计，主要累加器和相位/幅度转换两部分组成。
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基于DDS的精密正弦信号发生器的设计
DDS功能模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity dds is
generic(width:integer:=8);
(m:in std_logic_vector(width:1 downto 0); sin,acc:out std_logic_vector(7 downto 0); clk:in std_logic); end dds;
architecture dds_arc of dds is
signal s,acc8:std_logic_vector(width:1 downto 0); signal msbs:std_logic_vector (7 downto 0); begin
add1:lam_add_sub
generic map(lpm_width=>width, lpm_representation=>\ lpm_direction=>\ lpm_pipeline=>0) port map(dataa=>m, datab=>acc8,result=>s); reg1:lpm_ff
generic map(lpm_width=>width)
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基于DDS的精密正弦信号发生器的设计
port
map(data=>s,q=>acc8,clock=>clk); select1:process(acc8), variable i:integer; begin
for i in 7 downto 0 loop msbs(i)<=acc8(i); end loop; end process select1; acc<=msbs; room1:lpm_rom
generic map(lpm_width=>8, lpm_widthad=>8, lpm_file=>\port map(adress=>msbs, inclock=>clk, outclock=>clk, q=>sin); end dds_arc;
相位累加器的VHDL设计：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity leijia is port
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