附录F 数码管显示模块RTL视图
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图F1 RTL视图
附录G 警告模块的Verilog HDL语言描述
always@(posedge iclk,negedge irst) begin if (!irst)
LED_warning_r <= 0;
else if(STOP == 1)
LED_warning_r <= 0;
else case (set_r) 2'b01 : if(omoney_r <3)
LED_warning_r <= 1;
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else
LED_warning_r <= 0;
2'b10 : if(omoney_r <6)
LED_warning_r <= 1;
else
LED_warning_r <= 0;
2'b11 : if(omoney_r <12)
LED_warning_r <= 1;
else
LED_warning_r <= 0;
endcase
end
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