AD9221/AD9223/AD9220
can be detected. Table V is a truth table for the over/underrangecircuit in Figure 28, which uses NAND gates. Systems requiringprogrammable gain conditioning of the AD9221/AD9223/AD9220 input signal can immediately detect an out-of-rangecondition, thus eliminating gain selection iterations. Also, OTRcan be used for digital offset and gain calibration.Table V.Out-of-Range Truth TableIn the equation, the rms aperture jitter, tA, represents the root-sum square of all the jitter sources, which include the clockinput, analog input signal, and A/D aperture jitter specification.For example, if a 5 MHz full-scale sine wave is sampled by anA/D with a total rms jitter of 15 ps, the SNR performance of theA/D will be limited to 66.5 dB. Undersampling applications areparticularly sensitive to jitter.The clock input should be treated as an analog signal in caseswhere aperture jitter may affect the dynamic range of the AD9221/AD9223/AD9220. As such, supplies for clock drivers should beseparated from the A/D output driver supplies to avoid modulatingthe clock signal with digital noise. Low jitter crystal controlledoscillators make the best clock sources. If the clock is generatedfrom another type of source (by gating, dividing, or other method),it should be retimed by the original clock at the last step.Most of the power dissipated by the AD9221/AD9223/AD9220is from the analog power supplies. However, lower clock speedswill reduce digital current slightly. Figure 29 shows the relation-ship between power and clock rate for each A/D.666462605856545250480.51.01.52.02.53.05V p-p2V p-pOTR0011MSBOTRMSBMSB0101Analog Input IsIn RangeIn RangeUnderrangeOverrangeOVER = “1”UNDER = “1”Figure 28.Overrange or Underrange LogicDigital Output Driver Considerations (DVDD)The AD9221, AD9223 and AD9220 output drivers can beconfigured to interface with 5 V or 3.3 V logic families by settingDVDD to 5 V or 3.3 V respectively. The AD9221/AD9223/AD9220 output drivers are sized to provide sufficient outputcurrent to drive a wide variety of logic families. However, largedrive currents tend to cause glitches on the supplies and mayaffect SINAD performance. Applications requiring the AD9221/AD9223/AD9220 to drive large capacitive loads or large fanoutmay require additional decoupling capacitors on DVDD. Inextreme cases, external buffers or latches may be required.Clock Input and ConsiderationsPOWER – mWPOWER – mWThe AD9221/AD9223/AD9220 internal timing uses the twoedges of the clock input to generate a variety of internal timingsignals. The clock input must meet or exceed the minimumspecified pulsewidth high and low (tCH and tCL) specificationsfor the given A/D as defined in the Switching Specifications tomeet the rated performance specifications. For example, theclock input to the AD9220 operating at 10 MSPS may have aduty cycle between 45% to 55% to meet this timing requirementsince the minimum specified tCH and tCL is 45 ns. For clockrates below 10 MSPS, the duty cycle may deviate from thisrange to the extent that both tCH and tCL are satisfied.All high speed high resolution A/Ds are sensitive to the qualityof the clock input. The degradation in SNR at a given full-scaleinput frequency (fIN) due to only aperture jitter (tA) can becalculated with the following equation: CLOCK FREQUENCY – MHzFigure 29a. AD9221 Power Consumption vs. ClockFrequency12512011511010510095905V p-p2V p-pSNR=20log10[1/2πfINtA]0123456CLOCK FREQUENCY – MHz
Figure 29b. AD9223 Power Consumption vs. ClockFrequencyREV. E–21–
AD9221/AD9223/AD9220
300280INPUT = 5V p-pPOWER – mW260impedance over a wide frequency range. Note that theAVDD and AVSS pins are co-located on the AD9221/AD9223/AD9220 to simplify the layout of the decouplingcapacitors and provide the shortest possible PCB tracelengths. The AD9221/AD9223/AD9220/EB power planelayout, shown in Figure 40 depicts a typical arrangementusing a multilayer PCB.INPUT = 2V p-p26AVDD2402200.1?F25AVSSAD9221/AD9223/AD9220200024681012140.1?F15AVDD16AVSSCLOCK FREQUENCY – MHzFigure 29c. AD9220 Power Consumption vs. ClockFrequencyFigure 30.Analog Supply DecouplingGROUNDING AND DECOUPLINGAnalog and Digital GroundingProper grounding is essential in any high speed, high resolutionsystem. Multilayer printed circuit boards (PCBs) are recom-mended to provide optimal grounding and power schemes. Theuse of ground and power planes offers distinct advantages:1.The minimization of the loop area encompassed by a signaland its return path.2.The minimization of the impedance associated with groundand power paths.3.The inherent distributed capacitor formed by the powerplane, PCB insulation, and ground plane.These characteristics result in both a reduction of electro-magnetic interference (EMI) and an overall improvement inperformance.It is important to design a layout that prevents noise from cou-pling onto the input signal. Digital signals should not be run inparallel with input signal traces and should be routed away fromthe input circuitry. While the AD9221/AD9223/AD9220 featuresseparate analog and digital ground pins, it should be treated asan analog component. The AVSS and DVSS pins must be joinedtogether directly under the AD9221/AD9223/AD9220. A solidground plane under the A/D is acceptable if the power andground return currents are managed carefully. Alternatively,the ground plane under the A/D may contain serrations to steercurrents in predictable directions where cross-coupling betweenanalog and digital would otherwise be unavoidable. The AD9221/AD9223/AD9220/EB ground layout, shown in Figure 39, depictsthe serrated type of arrangement. The analog and digital groundsare connected by a jumper below the A/D.Analog and Digital Supply DecouplingThe CML is an internal analog bias point used internally by theAD9221/AD9223/AD9220. This pin must be decoupled with atleast a 0.1 μF capacitor as shown in Figure 31. The dc level ofCML is approximately AVDD/2. This voltage should be buff-ered if it is to be used for any external biasing.AD9221/AD9223/AD922022CML0.1?FFigure 31.CML DecouplingThe digital activity on the AD9221/AD9223/AD9220 chip fallsinto two general categories: correction logic and output drivers.The internal correction logic draws relatively small surges ofcurrent, mainly during the clock transitions. The output driversdraw large current impulses while the output bits are changing.The size and duration of these currents are a function of theload on the output bits: large capacitive loads are to be avoided.Note, the internal correction logic of the AD9221, AD9223,and AD9220 is referenced to AVDD while the output driversare referenced to DVDD.The decoupling shown in Figure 32, a 0.1 μF ceramic chipcapacitor, is appropriate for a reasonable capacitive load onthe digital outputs (typically 20 pF on each pin). Applicationsinvolving greater digital loads should consider increasing thedigital decoupling proportionally, and/or using external buff-ers/latches.28DVDD0.1?F27DVSSAD9221/AD9223/AD9220The AD9221/AD9223/AD9220 features separate analog anddigital supply and ground pins, helping to minimize digitalcorruption of sensitive analog signals. In general, AVDD, theanalog supply, should be decoupled to AVSS, the analogcommon, as close to the chip as physically possible. Figure 30shows the recommended decoupling for the analog supplies;0.1 μF ceramic chip capacitors should provide adequately lowFigure 32.Digital Supply DecouplingA complete decoupling scheme will also include large tantalumor electrolytic capacitors on the PCB to reduce low frequencyripple to negligible levels. Refer to the AD9221/AD9223/AD9220/EB schematic and layouts in Figures 36 to 42 for moreinformation regarding the placement of decoupling capacitors.–22–REV. E
AD9221/AD9223/AD9220
APPLICATIONSDirect IF Down Conversion Using the AD922090807060SNR/SFDR – dBAs previously noted, the AD9220’s performance in the differen-tial mode of operation extends well beyond its baseband regionand into several Nyquist zone regions. Thus, the AD9220 maybe well suited as a mix down converter in both narrow andwideband applications. Various IF frequencies exist over thefrequency range in which the AD9220 maintains excellentdynamic performance (e.g., refer to Figure 17 and 18). The IFsignal will be aliased to the ADC’s baseband region due to thesampling process in a similar manner that a mixer will down-convert an IF signal. For signals in various Nyquist zones, thefollowing equation may be used to determine the final frequencyafter aliasing. f1 NYQUIST = fSIGNAL f2 NYQUIST = fSAMPLE – fSIGNAL f3 NYQUIST = abs (fSAMPLE – fSIGNAL) f4 NYQUIST = 2 × fSAMPLE – fSIGNAL f5 NYQUIST = abs (2 × fSAMPLE – fSIGNAL)There are several potential benefits in using the ADC to alias(i.e., or mix) down a narrow-band or wideband IF signal. Firstand foremost is the elimination of a complete mixer stage withits associated amplifiers and filters, reducing cost and powerdissipation. Second is the ability to apply various DSP tech-niques to perform such functions as filtering, channel selection,quadrature demodulation, data reduction, and detection.One common example is the digitization of a 21.4 MHz IFusing a low jitter 10 MHz sample clock. Using the equationabove for the fifth Nyquist zone, the resultant frequency aftersampling is 1.4 MHz. Figure 33 shows the typical performanceof the AD9220 operating under these conditions. Figure 34demonstrates how the AD9220 is still able to maintain a highdegree of linearity and SFDR over a wide amplitude.01 SFDR 50 SNR 403020100–50–40–30–20AIN – dB–100Figure 34. AD9220 Differential Input SNR/SFDRvs. Input Amplitude (AIN) @ 21.4 MHzMultichannel Data Acquisition with AutocalibrationThe AD9221/AD9223/AD9220 is well suited for high perfor-mance, low power data acquisition systems. Aside from itsexceptional ac performance, it exhibits true 12-bit linearity andtemperature drift performance (i.e., excluding internal refer-ence). Furthermore, the A/D product family provides the systemdesigner with an upward or downward component selectionpath based on power consumption and sampling rate.A typical multichannel data acquisition system is shown inFigure 35. Also shown is some additional inexpensive gain andoffset autocalibration circuitry that is often required in highaccuracy data acquisition systems. These additional peripheralcomponents were selected based on their performance, powerconsumption, and cost.Referring to Figure 35, the AD9221/AD9223/AD9220 is config-ured for single-ended operation with a 2.5 V p-p input span anda 2.5 V common-mode voltage using an external, precision 2.5voltage reference, U1. This configuration and input span allowsthe buffer amplifier, U4, to be single supply. Also, it simplifiesthe design of the low temperature drift autocalibration circuitrythat uses thin-film resistors for temperature stability and ratio-metric accuracy. The input of the AD9221/AD9223/AD9220can be easily configured for a wider span but it should remainwithin the input/output swing capabilities of a high speed, rail-to-rail, single-supply amplifier, U4 (e.g., AD8041).The gain and offset calibration circuitry is based on two 8-bit,current-output DAC08s, U3 and U5. The gain calibrationcircuitry consisting of U3, and an op amp, U2A, is configuredto provide a low drift nominal 1.25 V reference to the AD9221/AD9223/AD9220. The resistor values that set the gain calibra-tion range were selected to provide a nominal adjustment spanof ±128 LSBs with 1 LSB resolution with respect to the A/D. Notethat the bandwidth of the reference is low and, as a result, it isnot possible to change the reference voltage rapidly in this mode.–20 ENCODE = 10MSPS AIN = 21.4MHzAMPLITUDE – dB–40–60–8078692534–100–1201FREQUENCY – MHz5Figure 33.IF Sampling a 21.4 MHz Input Usingthe AD9220 (VCM = 2.5 V, Input Span = 2 V p-p)REV. E–23–
AD9221/AD9223/AD9220
The offset calibration circuitry consists of a DAC, U5 andthe buffer amplifier, U4. The DAC is configured for a bipolaradjustment span of ±64 LSB with a 1/2 LSB resolution spanwith respect to the AD9221/AD9223/AD9220. Note that bothcurrent outputs of U5 were configured to provide a bipolaradjustment span. Also, RC is used to decouple the output ofboth DACs, U3 and U5, from their respective op amps.The calibration procedure consists of a two step process. First,the bipolar offset is calibrated by selecting CH2, the 2.5 V sys-tem reference, of the analog multiplexer and preloading the DAC,U5, with a midscale code of 1000 0000. If possible, severalreadings of the A/D should be taken and averaged to determinethe required digital offset adjustment code, U5. This averagedoffset code requires an extra bit of resolution since 1 LSB of U5equates to 1/2 LSB of the AD9221/AD9223/AD9220. Therequired offset correction code to U5 can then be determined.Second, the system gain is calibrated by selecting CH2, a 1.25 V0.1?Finput that corresponds to –FS of the A/D. Before the value isread, U4 should be preloaded with a code of 00 (Hex). Severalreadings can also be taken and averaged to determine the digitalgain adjustment code to U2A. In this case, 1 LSB of the A/Dcorresponds to 1 LSB of U4.Due to the AD9221/AD9223/AD9220’s excellent INL perfor-mance, a two-point calibration procedure (i.e., –FS to midscale)instead of an endpoint calibration procedure was chosen. Also,since the bipolar offset is insensitive to any gain adjustment (dueto the differential SHA of the A/D), an iterative calibrationprocess is not required. The temperature stability of the circuitis enhanced by selecting a dual precision op amp for U2 (e.g.,OP293) and low temperature drift, thin film resistors. Note thatthis application circuit was not built at the release of this datasheet. Please consult Analog Devices for application assistanceor comments.1.25k?1.25VU2B2.5k?2.5k?0.1?F2.5k?162?2.5k?0.1?F1.1k?2 ? 39?+5VSENSERC100?VREFIOUTU2A1.25V?39mVCH1CH2CH3CH4CH6CH7CH80.1?F10?FU1REF432.5k?VREF(+)IOUTU6CH5ADG608OUTVREF(–)2.5k?U3DAC08AD9221/AD9223/AD922039?VINA39?VINBBIT 1 – BIT 12OTRU42.50V2.5k?VREF(+)VREF(–)2.5k?RC100?RC100?U5DAC08IOUTIOUTFigure 35.Typical Multichannel Data Acquisition System–24–REV. E
