Q:out std_logic_vector(7 downto 0)); end entity sin; architecture s of sin is
signal tmp: integer range 0 to 63; signal d:integer range 0 to 255; begin
process(clk,reset)is begin
if(reset='1') then tmp<=31; elsif(clk'event and clk='1') then
if(tmp=63) then
tmp<=0;
else
tmp<=tmp+1;
end if; case tmp is
when 00=>d<=255;when 01=>d<=254;when 02=>d<=252; when 03=>d<=249;when 04=>d<=245;when 05=>d<=239; when 06=>d<=233;when 07=>d<=225;when 08=>d<=217; when 09=>d<=207;when 10=>d<=197;when 11=>d<=186; when 12=>d<=174;when 13=>d<=162;when 14=>d<=150; when 15=>d<=137;when 16=>d<=124;when 17=>d<=112; when 18=>d<=99;when 19=>d<=87;when 20=>d<=75; when 21=>d<=64;when 22=>d<=53;when 23=>d<=43; when 24=>d<=34;when 25=>d<=26;when 26=>d<=19; when 27=>d<=13;when 28=>d<=8;when 29=>d<=4; when 30=>d<=1;when 31=>d<=0;when 32=>d<=0; when 33=>d<=1;when 34=>d<=4;when 35=>d<=8; when 36=>d<=13;when 37=>d<=19;when 38=>d<=26;
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when 39=>d<=34;when 40=>d<=43;when 41=>d<=53; when 42=>d<=64;when 43=>d<=75;when 44=>d<=87; when 45=>d<=99;when 46=>d<=112;when 47=>d<=124; when 48=>d<=137;when 49=>d<=150;when 50=>d<=162; when 51=>d<=174;when 52=>d<=186;when 53=>d<=197; when 54=>d<=207;when 55=>d<=217;when 56=>d<=225; when 57=>d<=233;when 58=>d<=239;when 59=>d<=245; when 60=>d<=249;when 61=>d<=252;when 62=>d<=254; when 63=>d<=255;when others=>null;
end case;
end if;
Q<=conv_std_logic_vector(d,8); end process; end architecture s;
------------------方波------------------------------------------------------------------------------------------- library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity squ is
port(clk ,reset: in std_logic; Q:out std_logic_vector(7 downto 0)); end entity squ; architecture s of squ is signal cc: integer range 0 to 9;
signal tmp: std_logic_vector(7 downto 0); begin
process (clk,reset) is begin
if(reset='1') then tmp<=\
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elsif(clk'event and clk='1') then
if(cc<9) then
cc<=cc+1;
else
cc<=0;
end if;
if cc=9 then tmp<=tmp xor \end if;
end if;
Q<=tmp; end process; end architecture s;
-------------波形选择------------------------------------------------------------------------------------------ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity chs is
port(ob,si,dl,sq: in std_logic;
obl,sin,dlt,squ: in std_logic_vector(7 downto 0);
Q:out std_logic_vector(7 downto 0)); end entity chs; architecture ch of chs is
signal tmp: std_logic_vector(3 downto 0); signal tt:std_logic_vector(9 downto 0); begin
process(ob,si,dl,sq)is begin
tmp<=ob&si&dl&sq; case tmp is
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when \when \when \when \
when \when \when \ when \when \when \when others=>null;
end case; end process; end architecture ch;
------------调度程序-------------------------------------------------------------------------------------------- --------------开始------------------------------------------------------------------------------------------------ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------------------------------------------- entity s_gen is
port(clk ,reset: in std_logic;
ob,si,dl,sq: in std_logic;
tc: in std_logic_vector(1 downto 0); a,b,c,d,e,f,g:out std_logic;
wr:out std_logic;
Q:out std_logic_vector(7 downto 0)); end entity s_gen;
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