ALUOp=3'b000; IRWrite=0; PCWrite=0; end s2:begin ALUSrcA=1; ALUSrcB=2'b10; ALUOp=3'b000; IRWrite=0; PCWrite=0; end s3:begin lorD=1; end s4:begin RegDst=0; MemtoReg=1; RegWrite=1; end s5:begin lorD=1; MemWrite=1; end s6:begin ALUSrcA=1; ALUSrcB=2'b00; ALUOp=3'b000;//??? end s7:begin RegDst=1; MemtoReg=0; RegWrite=1; end s8:begin ALUSrcA=1; ALUSrcB=2'b00; ALUOp=3'b111; PCSrc=2'b01; Branch=1; end s9:begin ALUSrcA=1; ALUSrcB=2'b10; ALUOp=3'b000;
end s10:begin RegDst=0; MemtoReg=0; RegWrite=1; end s11:begin PCSrc=2'b10; PCWrite=1; end endcase end endmodule
【仿真源码】
module TestTop;
// Inputs reg clk; reg reset;
// Outputs wire[31:0] PC; wire[31:0] Instr;
// Instantiate the Unit Under Test (UUT) Top uut ( .clk(clk), .reset(reset), .PC(PC), .Instr(Instr) );
initialbegin
// Initialize Inputs clk =0; reset =0; #5;// 刚开始设置pc为0 clk =!clk; #5;
reset =1; clk =!clk; forever#5 clk =!clk; end endmodule
