附录C
附录B (频率运算控制模块代码)
module ys(data_in,data_out,q,c,led); input [27:0] data_in; output [9:0] q; output [3:0] c;
output [22:0] data_out; output [1:0] led; reg [9:0] q; wire [3:0] c;
wire [22:0] data_out; wire [1:0] led;
assign led=(data_in<1000000)?2'b01:2'b10; assign data_out[22:0]=data_in[22:0]; assign c=10;
always @(data_in) begin
if(data_in<10000) q=1;
else if(data_in<100000) q=10; else if(data_in<1000000) q=100; else q=1000; end
endmodule
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附录D
附录C (FPGA核心板原理图)
图1 FPGA核心板1
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