);
end eight_tri; architecture a of eight_tri is
signal sel: std_logic_vector(8 downto 0); begin
sel<=en & b;
y<= “000” when (sel=”100000001”)else “001” when (sel=”100000010”)else “010” when (sel=”100000100”)else “011” when (sel=”100001000”)else “100” when (sel=”100010000”)else “101” when (sel=”100100000”)else “110” when (sel=”101000000”)else “111” when (sel=”110000000”)else “zzz”; end a;
3、 试用VHDL描述一个外部特性如图所示的D触发器。（10分）
参考程序如下： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY mydff IS
PORT(CLK:IN STD_LOGIC; D:IN STD_LOGIC; Q:OUT STD_LOGIC); END;
ARCHITECTURE bhv OF mydff IS BEGIN
PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1' THEN Q<=D; END IF; END PROCESS; END;
4、 下图为某一状态机对应的状态图，试用VHDL语言描述这一状态机。（18分）
其它/00001/1001S0S1其它/10010/0000其它/1111S30/1100其它/11001/1111S2
参考程序如下： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY FSM2 IS
PORT ( clk,reset,in1 : IN STD_LOGIC;
out1 : OUT STD_LOGIC_VECTOR(3 downto 0)); END;
ARCHITECTURE bhv OF FSM2 IS TYPE state_type IS (s0, s1, s2, s3); SIGNALcurrent_ state,next_state: state_type; BEGIN
P1:PROCESS(clk,reset) BEGIN
IF reset = ‘1’ THEN current_state <= s0; ELSIF clk='1' AND clk'EVENT THEN
current_state <=next_state; END IF;
END PROCESS;
P2:PROCESS(current_state) BEGIN
case current_state is
WHEN s0 => IF in1=‘1’THEN next_state<=s1; ELSE next_state<=s0; END IF;
WHEN s1 => IF in1='0'THEN next_state<=S2; ELSE next_state<=s1; END IF;
WHEN s2 => IF in1='1'THEN next_state<=S3; ELSE next_state<=s2; END IF;
WHEN s3 => IF in1='0'THEN next_state<=S0;
ELSE next_state<=s3; END IF;
end case;
END PROCESS;
p3:PROCESS(current_state) BEGIN
case current_state is
WHEN s0 => IF in1=‘1’THEN out1<=“1001”; ELSE out1<=\ END IF; WHEN s1 => IF in1='0'THEN out1<=\ ELSE out1<=\ END IF; WHEN s2 => IF in1='1'THEN out1<=\ ELSE out1<=\ END IF; WHEN s3 => IF in1='1'THEN out1<=\ ELSE out1<=\ END IF; end case; END PROCESS; end bhv;
5、 数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面四种方式中的两种来描述该数据选择器MUX的结构体。
SEL(1:0)SEL00AIN(1:0)BIN(1:0)COUTA or BA xor BA and BA nor B“XX”MUXCOUT(1:0)011011OTHERS
(a) 用if语句。(b) 用case 语句。 (c) 用when else 语句。 (d) 用with select 语句。
Library ieee;
Use ieee.std_logic_1164.all;
Entity mymux is
Port ( sel : in std_logic_vector(1 downto 0); -- 选择信号输入 Ain, Bin : in std_logic_vector(1 downto 0); -- 数据输入 Cout : out std_logic_vector(1 downto 0) ); End mymux;
Architecture one of mymux is Begin
Process (sel, ain, bin) Begin If sel = “00” then cout <= ain or bin; Elsif sel = “01” then cout <= ain xor bin; Elsif sel = “10” then cout <= ain and bin; Else cout <= ain nor bin; End if; End process;
End one;
Architecture two of mymux is Begin
Process (sel, ain, bin) Begin Case sel is when “00” => cout <= ain or bin; when “01” => cout <= ain xor bin; when “10” => cout <= ain and bin; when others => cout <= ain nor bin; End case; End process; End two;
6、 根据下面原理图，写出相应VHDL描述
Library ieee;
Use ieee.std_logic_1164.all; Entity mycir is
Port (ain , bin , clk : in std_logic; Cout : out std_logic); End mycir;
Architecture one of mycir is Signal tb, tc; Begin
Process (clk) begin If clk?event and clk = ?1? then tb <= bin; end if; End process;
Process (clk, tc) begin
If clk = ?1? then cout <= tc;end if; End process; Tc <= ain xor tb; End one;
7、 用两种以上的按照下图设计一个四选一多路选择器
