Logisim实验
Because the RAM module doesn't look like the idealized memory we saw in lecture, you may feel confused about where to begin. The picture above shows a good way to wire up a circuit to use RAM. Here are a few things to know before you get started.
?
? ? ?
?
?
?
\determines whether or not the RAM module is active. We will probably not run into any cases where we need to turn our RAM off, so you can wire a constant 1 to this.
\
The clock input provides synchronization for memory writes. Be sure to use the same clock here as you do for your reg file.
\is high, then \will be driven with the contents of memory at address \
\will instantly set all contents of memory to 0 if high. You should wire a manual switch so you can clear out memory whenever you want to restart a test.
\have to be careful not to drive this line from two conflicting sources, which in this case are DataIn and the output of the memory. You can solve this by using a controlled buffer (aka a tri-state buffer) on the \port of the RAM module. By wiring logic to the \port of the controlled buffer together so that they are always opposite values (as in the picture above), we can prevent conflicts between data being driven in and the contents of memory coming out.
The \can also use right-click --> Load Image... to load an image from a file.
计算机组成与设计
模板版本：2.1 13 / 14
Logisim实验
6、 控制电路 Func Opcode RegDst nPCsel RegW MemW ALUSrc ExtOp ALUCtl1 ALUCtl0 ALUCtl Jump 00 000 Add 1(rd) 0 1 0 0 X 0 0 Add 0 01 000 Sub 1 0 1 0 0 0 X 0 1 Sub 0 We don’t care 001 Ori 0(rt) 0 1 0 0 1 0 1 0 Or 0 010 Lw 0 0 1 0 1 1 1 0 0 Add 0 011 Sw X 0 0 1 X 1 1 0 0 Add 0 100 Beq X 1 0 0 X 0 X 0 1 Sub 0 101 Jmp X X 0 0 X X X X X X 1 MemToReg 0 Rtype = ~opcode2 . ~opcode1. ~opcode0 Add = rtype . ~func1 . ~func0 Sub = rtype . ~func1. Func0 Ori = ~op2.~op1. op0 lw = ~op2.op1.~op0 sw = ~op2.op1.op0 beq = op2.~op1~op0 jmp = op2.~op1.op0
RegDst = add + sub nPCsel = beq
RegW = add + sub + ori + lw MemW = sw MemToReg = lw
ALUSrc = Ori + lw + sw ALUCtl1 = ori
ALUCtl0 = sub + beq Jump = jmp
7、 连接各个部件
计算机组成与设计
模板版本：2.1 14 / 14
